VLSI Design Intern at Apple India

Apple India is hiring a VLSI Design Intern in Gurugram for a 3-month, fully mentored internship. This is real, reviewed work on live projects — not a training sandbox or a certificate mill. About the internship You will join the silicon design team and work alongside people who do this professionally every day. From week one you own a scoped piece of work, take it through review, and see it ship. Day-to-day responsibilities • Write and simulate RTL modules in Verilog/VHDL. • Run functional verification against test benches. • Support timing and synthesis analysis on blocks. • Document design intent and verification results. • Document your work clearly so the next person can pick it up. • Take part in stand-ups, planning and review sessions with the team. Tools and technologies you will use VLSI, Verilog, VHDL, Digital Design, RTL, Cadence, Synopsys, Timing Analysis, Simulation, Semiconductors — plus the internal tooling Apple India uses day to day. What you will learn The silicon design flow from RTL through verification to timing closure, on tooling used across the semiconductor industry. Team structure You report to a senior team member who acts as your mentor, inside a pod of 6-10 people. Weekly 1:1s track progress and a mid-internship review tells you exactly where you stand. What we expect from you Curiosity, ownership and clear communication. You are not expected to know every tool listed — you are expected to have solid fundamentals, ask good questions, and document what you do. Details: ₹18,000/month stipend · 3 months · Work From Home (Remote) · 1 opening · Gurugram. If you want to start a career in VLSI design in Gurugram, apply now. Responsibilities: Write and simulate RTL modules in Verilog/VHDL.; Run functional verification against test benches.; Support timing and synthesis analysis on blocks.; Document design intent and verification results.; Document your work so the next person can pick it up. Requirements: Education: pursuing or completed B.E./B.Tech/M.Tech in Electronics, Electrical, VLSI or a related discipline; Graduation year: 2025, 2026 or 2027 batch; Minimum 60% / 6.0 CGPA (relaxable for candidates with strong practical projects); Technical skills: working knowledge of VLSI, Verilog, VHDL, Digital Design; Soft skills: clear written communication, ownership, willingness to document work; Experience: none required — freshers welcome; prior projects or certifications are a plus.